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june 2013 ? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsb117h / fsb127h / fsb147h ? rev. 1.0.7 fsb117h / fsb127h / fsbh147h ? mwsaver ? fairchild power switch (fps?) fsb117h / fsb127h / fsb147h mwsaver? fairchild power switch (fps?) features mwsaver? technology ? achieve low no-load power consumption less than 40 mw at 230 v ac (emi filter loss included) ? meets 2013 erp standby power regulation (less than 0.5 w consumption with 0.25 w load) for atx power and lcd tv power ? eliminate x-cap discharge resistor loss with ax-cap? technology ? linearly decreased switching frequency at light- load condition and advanced burst mode operation at no-load condition ? 700 v high-voltage jfet startup circuit to eliminate the startup resistor loss highly integrated with rich features ? internal avalanche-rugged 700 v sensefet ? built-in 5 ms soft-start ? peak-current-mode control ? cycle-by-cycle current limiting ? leading-edge blanking (leb) ? synchronized slope compensation ? proprietary asynchronous jitter to reduce emi advanced protection ? internal overload / open-loop protection (olp) ? v dd under-voltage lockout (uvlo) ? v dd over-voltage protection (ovp) ? constant power limit (full ac input range) ? internal auto restart circuit (olp, v dd ovp, otp) ? internal otp sensor with hysteresis ? adjustable peak current limit related resources ? evaluation board: febfsb127h_t001 ? fairchild power supply webdesigner ? flyback design & simulation - in minutes at no expense description the fsb-series is a next-generation, green-mode fairchild power switch (fps?) incorporating fairchild?s innovative mwsaver? technology, which dramatically reduces standby and no-load power consumption, enabling conformance to all worldwide standby mode efficiency guidelines. it integrates an advanced current- mode pulse width modulator (pwm) and an avalanche- rugged 700 v sensefet in a single package, allowing auxiliary power designs with higher standby energy efficiency, reduced size, improved reliability, and lower system cost than previous solutions. fairchild semiconductor? s mwsaver? technology offers best-in-class mini mum no-load and light-load power consumption. an innovative ax-cap? method, one of the five proprietary mwsaver? technologies, minimizes losses in the emi filter stage by eliminating the x-cap discharge resist ors while still meeting iec61010-1 safety requirement. mwsaver? green mode gradually decreases switching frequency as load decreases to minimize switching losses. a new proprietary asynchronous jitter decreases emi emission and built-in synchronized slope compensation allows stable peak-current-mode control over a wide range of input voltage. the proprietary internal line compensation ensures const ant output power limit over entire universal line voltage range. requiring a minimum number of external components, the fsb-series provides a basic platform that is well suited for the cost-effectiv e flyback converter design with low standby power consumption. applications general-purpose switched-mode power supplies and flyback power converters, including: ? auxiliary power supply for pc, server, lcd tv, and game console ? smps for vcr, svr, stb, dvd, and dvcd player, printer, facsimile, and scanner ? general adapter ? lcd monitor power / open-frame smps
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsb117h / fsb127h / fsb147h ? rev. 1.0.7 2 fsb117h / fsb127h / fsb147h ? mwsa ver? fairchild power switch (fps?) ordering information part number sensefet operating temperature range package packing method fsb117hny 1 a, 700 v -40c to +105c 8-pin, dual in-line package (dip) tube fsb127hny 2 a, 700 v FSB147HNY 4 a, 700 v application diagram figure 1. typical flyback application table 1. output power table (1) product 230 v ac 15% (2) 85-265 v ac adapter (3) open frame (4) adapter (3) open frame (4) fsb117h 10 w 15 w 9 w 13 w fsb127h 14 w 20 w 11 w 16 w fsb147h 23 w 35 w 17 w 26 w notes: 1. the maximum output power can be li mited by junction temperature. 2. 230 v ac or 100/115 v ac with voltage doubler. 3. typical continuous power in a non- ventilated enclosed adapter with suffici ent drain pattern of printed circuit board (pcb) as a heat sink, at 50 ? c ambient. 4. maximum practical continuous power in an open-frame des ign with sufficient drain pattern of printed circuit board (pcb) as a heat sink, at 50 ? c ambient.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsb117h / fsb127h / fsb147h ? rev. 1.0.7 3 fsb117h / fsb127h / fsb147h ? mwsa ver? fairchild power switch (fps?) internal block diagram fb gnd vdd ipk 4 hv startup 5.4v soft driver q s r 12v/6v uvlo green mode olp ovp delay debounce v dd-ovp 2 5 6,7,8 3 1 4.6v hv line voltage sample circuit brownout protection olp 3r olp comparator pwm comparator internal bias soft-start v limit slope compensation r current-limit comparator soft-start comparator olp drain i pk v limit current limit compensation s/h 3.5v ovp otp 50a z fb osc1 clock generator v max pwm pwm osc2 auto-re-start protection maximum duty cyclelimit figure 2. block diagram
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsb117h / fsb127h / fsb147h ? rev. 1.0.7 4 fsb117h / fsb127h / fsb147h ? mwsa ver? fairchild power switch (fps?) pin configuration figure 3. pin configuration pin definitions pin # name description 1 gnd ground. this pin internally connects to the s ensefet source and signal ground of the pwm controller. 2 vdd supply voltage of the ic. typically the holdup capacitor connects from this pin to ground. rectifier diode in series with the transformer auxiliary winding connects to this pin to supply bias during normal operation. 3 fb feedback. the signal from the external compensatio n circuit connects to this pin. the pwm duty cycle is determined by comparing the signal on this pin and the internal current-sense signal. 4 ipk adjust peak current. typically a resistor connects from this pin to the gnd pin to program the current-limit level. the internal current s ource (50 a) introduces voltage drop across the resistor, which determines the current limit level of pulse-by-pulse current limit. 5 hv startup. typically, resistors in series with diodes from the ac line connect to this pin to supply internal bias and to charge the external capacitor connected between the vdd pin and the gnd pin during startup. this pin is also used to se nse the line voltage for brownout protection and ac line disconnection detection. 6 drain sensefet drain. this pin is desi gned to directly drive the transformer. 7 8 f ? fairchild logo z ? plant code x ? 1-digit year code y ? 1-digit week code tt ? 2-digit die run code t ? package type (n: dip) p ? y: green package m ? manufacture flow code
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsb117h / fsb127h / fsb147h ? rev. 1.0.7 5 fsb117h / fsb127h / fsb147h ? mwsa ver? fairchild power switch (fps?) absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v drain drain pin voltage (5,6) 700 v i dm drain current pulsed (7) fsb117h 4.0 a fsb127h 8.0 fsb147h (9) 9.6 e as single pulsed avalanche energy (8) fsb117h 50 mj fsb127h 140 fsb147h 120 v dd dc supply voltage 30 v v fb fb pin input voltage -0.3 7.0 v v ipk ipk pin input voltage -0.3 7.0 v v hv hv pin input voltage 700 v p d power dissipation (t a 50c) 1.5 w t j operating junction temperature -40 internally limited (10) ? c t stg storage temperature range -55 +150 ? c t l lead soldering temperature (wave soldering or ir, 10 seconds) +260 ? c esd electrostatic discharge capability, all pins except hv pin human body model: jesd22-a114 5.50 kv charged device model: jesd22-c101 2.00 electrostatic discharge capability, all pins including hv pin human body model: jesd22-a114 3.00 charged device model: jesd22-c101 1.25 notes : 5. all voltage values, except differential voltages, ar e given with respect to the network ground terminal. 6. stresses beyond those listed under absolute maximu m ratings may cause permanent damage to the device. 7. non-repetitive rating: pulse width is limited by maximum junction temperature. 8. l=51 mh, starting t j =25c. 9. l=14 mh, starting t j =25c. 10. internally limited by over-temper ature protection (otp). refer to t otp . recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificatio ns. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit r hv resistor connect to hv pin for full range input detection 150 250 k ? thermal resistance table symbol parameter typ. unit ja junction-to-air thermal resistance 86 ? c/w jt junction-to-package thermal resistance (11) 20 ? c/w note : 11. measured on the package top surface.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsb117h / fsb127h / fsb147h ? rev. 1.0.7 6 fsb117h / fsb127h / fsb147h ? mwsa ver? fairchild power switch (fps?) electrical characteristics v dd =15 v, t a =25 ? c unless otherwise specified. symbol parameter condition min. typ. max. unit sensefet section (12) bv dss drain-source breakdown voltage i d =250a, v gs =0 v 700 v i dss zero-gate-voltage drain current v ds =700 v, v gs =0 v 50 a v ds =560 v, v gs =0 v, t c =125 ? c 200 r ds(on) drain-source on-state resistance (13) fsb117h v gs =10 v, i d =0.5 a 8.8 11.0 ? fsb127h 6.0 7.2 fsb147h v gs =10 v, i d =2.5 a 2.3 2.7 c iss input capacitance fsb117h v gs =0 v, v ds =25 v, f=1 mhz 250 325 pf fsb127h 550 715 fsb147h 450 500 c oss output capacitance fsb117h v gs =0 v, v ds =25 v, f=1 mhz 25 33 pf fsb127h 38 50 fsb147h 60 72 c rss reverse transfer capacitance fsb117h v gs =0 v, v ds =25 v, f=1 mhz 10 15 pf fsb127h 17 26 fsb147h 7 21 t d(on) turn-on delay fsb117h v ds =350 v, i d =1.0 a 12 34 ns fsb127h 20 50 fsb147h 12 35 t r rise time fsb117h v ds =350 v, i d =1.0 a 4 18 ns fsb127h 15 40 fsb147h 20 50 t d(off) turn-off delay fsb117h v ds =350 v, i d =1.0 a 30 70 ns fsb127h 55 120 fsb147h 30 70 t f fall time fsb117h v ds =350 v, i d =1.0 a 10 30 ns fsb127h 25 60 fsb147h 16 42 continued on the following page?
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsb117h / fsb127h / fsb147h ? rev. 1.0.7 7 fsb117h / fsb127h / fsb147h ? mwsa ver? fairchild power switch (fps?) electrical characteristics (continued) v dd =15 v, t a =25 ? c unless otherwise specified. symbol parameter condition min. typ. max. unit control section vdd section v dd-on uvlo start threshold voltage 11 12 13 v v dd-off1 uvlo stop threshold voltage 5 6 7 v v dd-off2 i dd-olp enable threshold voltage 8 9 10 v v dd-olp v dd voltage threshold for hv startup turn- on at protection mode 5 6 7 v i dd-st startup supply current v dd-on ? 0.16 v 30 a i dd-op1 operating supply current with normal switching operation v dd =15 v, v fb =3 v 3.8 ma i dd-op2 operating supply current without switching operation v dd =15 v, v fb =1 v 1.8 ma i dd-olp internal sinking current v dd-olp + 0.1 v 30 60 90 a v dd-ovp v dd over-voltage protection 27 28 29 v t d-vddovp v dd over-voltage protection debounce time 70 140 210 s hv section i hv supply current drawn from hv pin hv=120 v dc , v dd =0 v with 10 f 1.5 5.0 ma i hv-lc leakage current after startup hv=700 v, v dd =v dd-off1 +1 v 10 a v ac-on brown-in threshold level (v dc ) dc voltage applied to hv pin through 200 k ? resistor 105 110 115 v v ac-off brownout threshold level (v dc ) v ac-on -10 v t uvp brownout protection time 0.8 1.2 1.6 s oscillator section f osc frequency in nominal mode center frequency 94 100 106 khz hopping range 4.0 6.0 8.0 t hop hopping period (12) 20 ms f osc-g green-mode frequency 20 23 26 khz f dv frequency variation vs. v dd deviation v dd =11 v to 22 v 5 % f dt frequency variation vs. temperature deviation (12) t a =-40 to 105c 5 % continued on the following page?
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsb117h / fsb127h / fsb147h ? rev. 1.0.7 8 fsb117h / fsb127h / fsb147h ? mwsa ver? fairchild power switch (fps?) electrical characteristics (continued) v dd =15 v, t a =25 ? c unless otherwise specified. symbol parameter condition min. typ. max. unit feedback input section a v internal voltage dividing factor of fb pin (12) 1/4.5 1/4.0 1/3.5 v/v z fb pull-up impedance of fb pin 15 21 27 k ? v fb-open fb pin pull-up voltage fb pin open 5.2 5.4 5.6 v v fb-olp fb voltage threshold to trigger open-loop protection 4.3 4.6 4.9 v t d-olp delay of fb pin open-loop protection 46 56 66 ms v fb-n fb voltage threshold to exit green mode v fb is rising 2.4 2.6 2.8 v v fb-g fb voltage threshold to enter green mode v fb is falling v fb-n -0.2 v v fb-zdc fb voltage threshold to enter zero-duty state v fb is falling 1.95 2.05 2.15 v v fb-zdcr fb voltage threshold to exit zero-duty state v fb is rising v fb-zdc +0.1 v ipk pin section v ipk-open ipk pin open voltage 3.0 3.5 4.0 v v ipk-h internal upper clamping voltage of ipk pin 3 (12) v v ipk-l internal lower clamping voltage of ipk pin 1.5 (12) v i pk internal current source of ipk pin t a =-40 to 105c, v ipk =2.25 v 45 50 55 a i lmt-fl-h current limit plateau when i pk pin voltage is internally clamped to upper limit fsb117h v ipk =3 v, duty>40% 0.72 0.80 0.88 a fsb127h 0.90 1.00 1.10 fsb147h 1.35 1.50 1.65 i lmt-va-h initial current limit when i pk pin voltage is internally clamped to upper limit fsb117h v ipk =3 v, duty=0% i lmt-fl-h -0.20 a fsb127h i lmt-fl-h -0.25 fsb147h i lmt-fl-h - 0.37 i lmt-fl-l current limit plateau when i pk pin voltage is internally clamped to lower limit fsb117h v ipk =1.5 v, duty>40% 0.36 0.40 0.44 a fsb127h 0.45 0.50 0.55 fsb147h 0.67 0.75 0.83 i lmt-va-l initial current limit when i pk pin voltage is internally clamped to lower limit fsb117h v ipk =1.5 v, duty=0% i lmt-fl-l -0.10 a fsb127h i lmt-fl-l -0.12 fsb147h i lmt-fl-l - 0.18 continued on the following page?
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsb117h / fsb127h / fsb147h ? rev. 1.0.7 9 fsb117h / fsb127h / fsb147h ? mwsa ver? fairchild power switch (fps?) electrical characteristics (continued) v dd =15 v, t a =25c unless otherwise specified. symbol parameter condition min. typ. max. unit current-sense section (14) t pd current limit turn-off delay 100 200 ns t leb leading-edge blanking time 230 280 330 ns t ss soft-start time (12) 5 ms gate section (14) dcy max maximum duty cycle 70 % over-temperature protection section (otp) t otp junction temperature to trigger otp (12) 135 142 150 c ? t otp hysteresis of otp (12) 25 c notes: 12. guaranteed by design; not 100% tested in production. 13. pulse test: pulse width 300 s, duty 2%. 14. these parameters, although guarante ed, are tested in wafer-sort process.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsb117h / fsb127h / fsb147h ? rev. 1.0.7 10 fsb117h / fsb127h / fsb147h ? mwsa ver? fairchild power switch (fps?) typical characteristics figure 4. v dd-on vs. temperature figure 5. v dd-off1 vs. temperature figure 6. v dd-off2 vs. temperature figure 7. v dd-ovp vs. temperature figure 8. v dd-lh vs. temperature figure 9. i dd-op1 vs. temperature figure 10. v ac-on vs. temperature figure 11. v ac-on ? v ac-off vs. temperature
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsb117h / fsb127h / fsb147h ? rev. 1.0.7 11 fsb117h / fsb127h / fsb147h ? mwsa ver? fairchild power switch (fps?) typical characteristics figure 12. v fb-open vs. temperature figure 13. v fb-olp vs. temperature figure 14. z fb v s. temperature figure 15. i pk vs. temperature figure 16. f osc vs. temperature figure 17. f osc-g vs. temperature
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsb117h / fsb127h / fsb147h ? rev. 1.0.7 12 fsb117h / fsb127h / fsb147h ? mwsa ver? fairchild power switch (fps?) functional description startup operation the hv pin is typically connected to the ac line input through two external diodes and one resistor (r hv ), as shown in figure 18. when the ac line voltage is applied, the v dd hold-up capacitor is charged by the line voltage through the diodes and resistor. after v dd voltage reaches the turn-on threshold voltage (v dd-on ), the startup circuit charging v dd capacitor is switched off and v dd is supplied by the auxiliary winding of the transformer. once the fsb-series starts, it continues operation until v dd drops below 6 v (v dd-off1 ). the ic startup time with a given ac line input voltage is: 22 ln 22 ac in startup hv dd a cin ddon v trc vv ? ? ? ?? ? ??? ?? (1) figure 18. startup circuit brown-in/out function the hv pin can detect the ac line voltage using a switched voltage divider that consists of external resistor (r hv ) and internal resistor (r ls ), as shown in figure 18. the internal line sensing circuit detects the real rms value of the line voltage using sampling circuit and peak detection circuit. since the voltage divider causes power consumption w hen it is switched on, the switching is driven by a signal with a very narrow pulse width to minimize power loss. the sampling frequency is adaptively changed according to the load condition to minimize the power consumption in light-load condition. based on the detected line voltage, brown-in and brownout thresholds are determined. since the internal resistor (r ls ) of the voltage divider is much smaller than r hv , the thresholds are given as: () 200 2 a con hv brown in v r vrms k ? ? ?? (2) () 200 2 a coff hv brown out v r vrms k ? ? ?? (3) pwm control the fsb-series employs current-mode control, as shown in figure 19. an opto-coupler (such as the h11a817a) and shunt regulator (such as the ka431) are typically used to implement the feedback network. comparing the feedback voltage with the voltage across the r sense resistor makes it possible to control the switching duty cycle. a synchronized positive slope is added to the sensefet current information to guarantee stable current-mode control ov er a wide range of input voltage. the built-in slope compensation stabilizes the current loop and prevents sub-harmonic oscillation. figure 19. current mode control soft-start the fsb-series has an internal soft-start circuit that progressively increases the pulse-by-pulse current limit level of mosfet during start up to establish the correct working conditions for transformers and capacitors, as shown in figure 20. the current limit levels have nine steps, as shown in figure 21. this prevents transformer saturation and reduces stress on the secondary diode during startup. figure 20. soft-start and current-limit circuit
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsb117h / fsb127h / fsb147h ? rev. 1.0.7 13 fsb117h / fsb127h / fsb147h ? mwsa ver? fairchild power switch (fps?) figure 21. current limit variation during soft-start adjustable peak current limit & h/l line compensation for constant power limit to make the limited output power constant regardless of the line voltage conditi on, a special current-limit profile with sample and hold is used (as shown in figure 22). the current-limit level is sampled and held at the falling edge of gate drive signal as shown in figure 23. then, the sampled current limit level is used for the next switching cycle. the sample-and-hold function prevents sub-harmonic oscillation in current- mode control. the current-limit level increases as the duty cycle increases, which reduces the current limit as duty cycle decreases. this allows lower current-limit level for high- line voltage condition where the duty cycle is smaller than that of low line. ther efore, the limited maximum output power can remain constant even for a wide input voltage range. the peak current limit is programmable using a resistor on the ipk pin. the internal current 50 a source for the ipk pin generates voltage drop across the resistor. the voltage of the ipk pin determi nes the current-limit level. since the upper and lower clamping voltage of the ipk pin are 3 v and 1.5 v, respectively, the suggested resistor value is from 30 k ? to 60 k ? . figure 22. i lmt vs. pwm turn-on time figure 23. current limit variation with duty cycle mwsaver? technology ax-cap ? to remove x-cap discharge resistor the emi filter in the front end of the switched mode power supply typically includes a capacitor across the ac line connector, as shown in figure 24. most of the safety regulations, such as ul 1950 and iec61010-1, require the capacitor be discharged to a safe level within a given time after unplugged from the power outlet. typically a discharge resister across the capacitor is used to ensure the capacitor is discharged naturally, which however introduces power loss of the power supply. as power level increases, the emi filter capacitor tends to increase, requiring a smaller discharge resistor to maintain same discharge ti me. this typically results in more power dissipation in high-power applications. the innovative ax-cap? technolo gy intelligently discharges the filter capacitor only when the power supply is unplugged from the power outlet. since the ax-cap? discharge circuit is disabled in normal operation, the power loss in the emi filter size can be virtually removed. figure 24. ax-cap? circuit green mode the fsb-series modulates the pwm frequency as a function of fb voltage, as shown in figure 25. since the output power is proportional to the fb voltage in current- mode control, the switching frequency decreases as load decreases. in heavy-load conditions, the switching frequency is 100 khz. once v fb decreases below v fb-n (2.6 v), the pwm frequency linearly decreases from 100 khz to 23 khz to reduce switching losses at light- load condition. as v fb decreases to v fb-g (2.4 v), the switching frequency is fixed at 23 khz. as v fb falls below v fb-zdc (2.1 v), the fsb-series enters burst mode operation, where pwm switching is disabled. then, the output volt age starts to drop, causing the feedback voltage to rise. once v fb rises above v fb- zdcr , switching resumes. burst mode alternately enables and disables switching, thereby reducing switching loss to reduce power consumption, as shown in figure 26. figure 25. pwm frequency
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsb117h / fsb127h / fsb147h ? rev. 1.0.7 14 fsb117h / fsb127h / fsb147h ? mwsa ver? fairchild power switch (fps?) figure 26. burst-mode operation protections the fsb-series provides protection function, that include overload / open-loop protection (olp), over- voltage protection (ovp), and over-temperature protection (otp). all the pr otections are implemented as auto-restart mode. once the fault condition is detected, switching is terminated and the sensefet remains off. this causes v dd to fall. when v dd falls to 6 v, the protection is re set and hv startup circuit charges v dd up to 12 v, allowing re-startup. open-loop / overload protection (olp) because of the pulse-by-pulse current-limit capability, the maximum peak current through the sensefet is limited and maximum input power is limited. if the output consumes more than the limited maximum power, the output voltage (v o ) drops below the set voltage. then the current through the opto-coupler led and the transistor become virtually zero and fb voltage is pulled high as shown in figure 27. if feedback voltage is above 4.6 v for longer than 56 ms, olp is triggered. this protection is also triggered when the feedback loop is open due to a soldering defect. . figure 27. olp operation v dd over-voltage protection (ovp) if the secondary-side feedback circuit malfunctions or a solder defect causes an op ening in the feedback path, the current through the opto- coupler transistor becomes virtually zero. then feedback voltage climbs up in a similar manner to the overload situation, forcing the preset maximum current to be supplied to the smps until the overload protection triggers. because more energy than required is provided to the output, the output voltage may exceed th e rated voltage before the overload protection triggers, resulting in the breakdown of the devices in the second ary side. to prevent this situation, an ovp circuit is employed. since v dd voltage is proportional to the output voltage by the transformer coupling, the over voltage of output is indirectly detected using v dd voltage. the ovp is triggered when v dd voltage reaches 28 v. debounce time (typically 150 s) is applied to prevent false triggering by switching noise. over-temperature protection (otp) the sensefet and the control ic are integrated in one package. this makes it easy fo r the control ic to detect the abnormal over temperature of the sensefet. if the temperature exceeds approxim ately 140c, the otp is triggered and the mosfet remains off. when the junction temperature drops by 25c from otp temperature, the fsb-series resumes normal operation. two-level uvlo since all the protections of the fsb-series are auto- restart, the power supply repeats shutdown and re- startup until the fault condition is removed. fsb-series has two-level uvlo, which is enabled when protection is triggered, to delay the re-startup by slowing down the discharge of v dd . this effectively reduces the input power of the power supply during the fault condition, minimizing the voltage/current stress of the switching devices. figure 28 shows the normal uvlo operation and two-step uvlo operation. when v dd drops to 6 v without triggering the protection, pwm stops switching and v dd is charged up by the hv startup circuit. meanwhile, when the protecti on is triggered, fsb-series has a different v dd discharge profile. once the protection is triggered, the ic stops switching and v dd drops. when v dd drops to 9 v, the operating current becomes very small and v dd is slowly discharged. when v dd is naturally discharged down to 6 v, the protection is reset and v dd is charged up by the hv startup circuit. once v dd reaches 12 v, the ic resumes switching operation. figure 28. two-level uvlo
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsb117h / fsb127h / fsb147h ? rev. 1.0.7 15 fsb117h / fsb127h / fsb147h ? mwsa ver? fairchild power switch (fps?) typical application circuit application fairchild devices input voltage range output standby auxiliary power fsb127h 85 v ac ~ 265 v ac 5 v / 3.2 a figure 29. schematic of typical application circuit
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsb117h / fsb127h / fsb147h ? rev. 1.0.7 16 fsb117h / fsb127h / fsb147h ? mwsa ver? fairchild power switch (fps?) typical application circuit (continued) transformer specification ? core: ei 22 ? bobbin: ei 22 ei - 22 n p /2 n 5v n a 1 2 3 4 5 6 10 n p /2 figure 30. transformer specification pin (s f) wire turns winding method n a 4 5 0.15 1 12 solenoid winding insulation: polyester tape t = 0.025 mm, 1-layer n p /2 3 2 0.27 1 31 solenoid winding insulation: polyester tape t = 0.025 mm, 2-layer n 5v 6 10 0.55 2 5 solenoid winding insulation: polyester tape t = 0.025 mm, 2-layer n p /2 2 1 0.27 1 31 solenoid winding insulation: polyester tape t = 0.025 mm, 2-layer pin specification remark primary-side inductance 1 3 900 ? h 10% 100 khz, 1 v primary-side effective leakage 1 3 < 30 ? h maximum short all other pins
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsb117h / fsb127h / fsb147h ? rev. 1.0.7 17 fsb117h / fsb127h / fsb147h ? mwsa ver? fairchild power switch (fps?) physical dimensions 85 4 1 notes: a) this package conforms to jedec ms-001 variation ba b) controling dims are in inches c) dimensions are exclusive of burrs, mold flash, and tie bar extrusions. d) dimensions and tolerances per asme y14.5m -1982 e) drawing filename and revsion: mkt-n08mrev1. 0.400 0.355 [ 10.160 9.017 ] 0.280 0.240 [ 7.112 6.096 ] 0.195 0.115 [ 4.965 2.933 ] min 0.015 [0.381] max 0.210 [5.334] 0.100 [2.540] 0.070 0.045 [ 1.778 1.143 ] 0.022 0.014 [ 0.562 0.358 ] 0.150 0.115 [ 3.811 2.922 ] c 0.015 [0.389] gage plane 0.325 0.300 [ 8.263 7.628 ] 0.300 [7.618] 0.430 [10.922] max 0.045 0.030 [ 1.144 0.763 ] 4x 4x 0.005 [0.126] min full lead 4x 0.005 [0.126] half lead 4x 0.10 c seating plane pin 1 indicator figure 31. 8-pin, dual in-line package (dip) package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsb117h / fsb127h / fsb147h ? rev. 1.0.7 18 fsb117h / fsb127h / fsb147h ? mwsa ver? fairchild power switch (fps?)

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